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Projet DeepAPMEA

Accelerating Processor for embedded MicroElectrode Array analysis using Deep Learning

Collaborators: Phillip Geier, Dr. Diego Barrientos,  Prof. Andres Upegui

In-vitro neural networks are cell cultures that permit a multiplicity of analysis useful for diagnostic purposes. Analysis on in-vitro neural networks can be studied through different types of sensing elements, among which, microelectrode arrays (MEA) are the most common. During a single experiment, MEA devices can generate huge amounts of data in the form of highly dimensional time series, which require specific analysis tools in order to extract useful data interpretable by biologists. The main goal of DeepAPMEA is to propose a digital hardware device endowed with state-of-the-art data analysis techniques. Two main issues will be addressed: (1) we will develop a set of methods for analyzing MEA data by using deep learning algorithms and (2) we will embed these algorithms in a hardware specific device based on FPGAs in order to perform data analysis.

The aim of this project is to design and implement a novel hardware device able to automatically perform analysis on multichannel time series. More precisely in the framework of DeepAPMEA we will target MEA data, but the proposed methodology and hardware architecture should be applicable to other application domains.

For achieving our goal we identify the following scientific and technical objectives:

  • We will develop a set of automatic tools based on LSTM networks for performing filtering and spike sorting on MEA raw data. This concerns data from a single electrode of the array.

  • We will explore the usability of LSTM networks in order to perform higher level analysis by analysing data from the complete array. The analysis of network dynamics will permit us to propose characterization or diagnostic tools based on pattern analysis on multiple spiking neurons.

  • Finally, these LSTM networks will be efficiently implemented on an FPGA with the goal of permitting a performant and low-power on-line and on-chip execution.